The integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit necessitates further dramatic scaling down or micro-miniaturization of the physical dimensions of circuit elements, including interconnection structures. Micro-miniaturization has engendered a dramatic increase in transistor engineering complexity, such as the inclusion of lightly doped drain structures, multiple implants for source/drain regions, silicidation of gates and source/drains, and multiple sidewall spacers, for example.
The drive for high performance requires high speed operation of microelectronic components requiring high drive currents in addition to low leakage, i.e., low off-state current, to reduce power consumption. Typically, the structural and doping parameters tending to provide a desired increase in drive current adversely impact leakage current.
Metal gate electrodes have evolved for improving the drive current by reducing polysilicon depletion. However, simply replacing polysilicon gate electrodes with metal gate electrodes may engender issues in forming the metal gate electrode prior to high temperature annealing to activate the source/drain implants, as at a temperature in excess of 900° C. This fabrication technique may degrade the metal gate electrode or cause interaction with the gate dielectric, thereby adversely impacting transistor performance.
Replacement metal gate (RMG) techniques have been developed to address problems attendant upon substituting metal gate electrodes for polysilicon gate electrodes. For example, a polysilicon dummy gate, formed on the substrate surrounded by spacers, is used during initial processing until high temperature annealing to activate source/drain implants has been implemented. Subsequently, an interlayer dielectric (ILD) is formed over the entire substrate, the polysilicon is removed, forming a cavity between the spacers, and a metal gate is formed in the cavity.
Additional issues arise with lateral scaling, such as the formation of contacts. For example, once the contacted poly pitch gets to about 80 nm, there is not enough room to land a contact between the gate lines and still maintain good electrical isolation properties between the gate line and the contact. SAC methodology has been developed to address this problem. A conventional SAC process insulates the gate metal from the contact metal by recessing the metal gate and inserting an insulating cap layer. The cap layer (e.g., silicon nitride (SiN)) insulates the gate metal from the partially overlapped contact metal. However, since the gate is formed of multiple metal layers (of different materials), effecting a uniform metal recess is a complicated process. Further, the material of the cap layer is susceptible to erosion during various subsequent processes, particularly the chemical mechanical polishing (CMP) of the ILD layer for a salicide process and during etching of the ILD for contact formation. Therefore, to obtain a sufficient/effective SAC cap (i.e., one having a thickness of at least 30 nm), a taller dummy gate is needed, which causes integration difficulties.
A need therefore exists for methodology enabling formation of a SAC on a non-recessed metal gate and the resulting device.